Flash memory is classified as non-volatile memory because a memory cell in the flash memory can retain the data stored in the memory cell without periodic refreshing. Most prior art flash memory can store a single bit in a memory cell. In other words, the memory cell can either store a "one" or a "zero".
Further, typical prior art flash memory cells are "two poly" processes, i.e., two distinct polysilicon deposition steps are required to form the cell. The most common structure for a flash memory cell is shown in FIG. 1. Further, typical prior art flash memory cells are "two poly" processes, i.e., two distinct polysilicon deposition steps are required to form the cell. In the most common structure for a flash memory cell shown in FIG. 1, a floating gate 101 comprised of polysilicon is formed atop of a thin gate oxide layer 103. A composite dielectric layer 111, such as oxide-nitride-oxide, is located atop the floating gate 101. The floating gate 101 and the composite dielectric layer 111 are in turn deposited and simultaneously patterned atop a semiconductor substrate 105. Finally, a control gate 113 comprised of polysilicon is formed atop the insulating oxide layer 111 and atop the floating gate 101. Adjacent the floating gate 101 are implanted source 107 and drain 109 regions.
In operation, the floating gate 101 can be in one of two states: (1) storing charge or (2) not storing charge. When the floating gate 101 is storing charge, the threshold voltage of the transistor will be shifted in the positive direction and a predetermined applied voltage applied to control gate 113 will not cause current to flow from the source 107 to the drain 109. When the floating gate 101 is not storing charge, the threshold voltage of the transistor will be shifted in the negative direction and the predetermined applied voltage applied to the control gate 113 will cause current to flow from the source 107 to the drain 109. In this manner, by using a "select transistor" (not shown) to measure the current from the source 107 to the drain 109 when a predetermined applied voltage is applied to the control gate 113, a determination can be made as to whether or not the floating gate 101 is carrying a charge, i.e., whether a "one" or a "zero" is being stored in the flash memory cell.
The process of placing a charge into the floating gate 101 ("writing") or removing a charge from the floating gate 101 ("erasing") is well known in the art and is simply the appropriate combination of applying voltages to the control gate 113, the source 107, and the drain 109. Further details of the flash memory cell of FIG. 1 may be found in Prince, "Semiconductor Memories: A Handbook of Design, Manufacture, and Application, 2nd Ed.," J. Wiley, 1991.
As seen in FIG. 1, the floating gate 101 requires the deposition of a first polysilicon layer and the control gate 113 requires the deposition of a second polysilicon layer. Additionally, the gate coupling ratio of the flash memory cell of FIG. 1 is relatively low. What is needed is a flash memory cell that may be manufactured using a single polysilicon layer and that provides a high coupling ratio.